Shift register and image display apparatus containing the same

ABSTRACT

A unit shift register includes first and second transistors for supplying low supply voltage to an output terminal. First and second control signals which are complementary to each other are input to first and second control terminals, respectively. A third transistor is connected between the first transistor and first control terminal, and a fourth transistor is connected between the second transistor and second control terminal. The third and fourth transistors each have its drain connected to the gate of each other in a crossed manner.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a shift register, and moreparticularly, to a shift register for use as a scanning-line drivingcircuit for an image display apparatus or the like, which is formed offield effect transistors of the same conductivity type only.

2. Description of the Background Art

An image display apparatus (hereinafter referred to as a “displayapparatus”) such as a liquid crystal display includes a display panel inwhich a plurality of pixels are arrayed in a matrix. A gate line(scanning line) is provided for each row of pixels (pixel line), andgate lines are sequentially selected and driven in a cycle of onehorizontal period of a display signal, so that a displayed image isupdated. As a gate-line driving circuit (scanning-line driving circuit)for sequentially selecting and driving pixel lines, i.e., gate lines, ashift register for performing a shift operation in one frame period of adisplay signal can be used.

To reduce the number of steps in the manufacturing process of a displayapparatus, such shift register used as the gate-line driving circuit ispreferably formed of field effect transistors of the same conductivitytype only. Accordingly, various types of shift registers formed of N- orP-type field effect transistors only and display apparatuses containingsuch shift registers have been proposed (e.g., “Highly Stable IntegratedGate Driver Circuit using a-Si TFT with Dual Pull-down Structure” SoonYoung Yoon, et al., SIC 05 DIGEST, pp. 348-351). As a field effecttransistor, a metal oxide semiconductor (MOS) transistor, a thin filmtransistor (TFT), or the like is used.

A shift register used for the gate-line driving circuit is formed of aplurality of shift registers provided for each pixel line, i.e., eachgate line connected in cascade (cascade-connected). For ease ofdescription, each of a plurality of shift registers constituting thegate-line driving circuit will be called “a unit shift register”throughout the present specification.

A typical unit shift register includes, in the output stage, an outputpull-up transistor connected between an output terminal and a clockterminal and an output pull-down transistor connected between the outputterminal and a reference voltage terminal. In such unit shift register,a clock signal input to the clock terminal with the output pull-uptransistor turned on and the output pull-down transistor turned off by apredetermined input signal is transmitted to the output terminal, sothat an output signal is output. In contrast, the output pull-uptransistor is turned off and the output pull-down transistor is turnedon during a period in which the input signal is not input, so that thevoltage level (hereinafter briefly called “level”) at the outputterminal is maintained at the L level.

A display apparatus employing amorphous silicon TFTs (a-Si TFTs) asshift registers of a gate-line driving circuit easily achieveslarge-area display with great productivity, and is widely used as thescreen of a notebook PC, a large-screen display apparatus, etc.

Conversely, an a-Si TFT tends to have its threshold voltage shifted inthe positive direction when the gate electrode is continuouslypositively biased (dc-biased), resulting in degraded driving capability(current-flowing capability). Particularly in a shift register of agate-line driving circuit, an operation in which the gate of the outputpull-down transistor is positively biased for about one frame period(about 16 ms) is continuously carried out, which gradually degrades theoutput pull-down transistor in driving capability. Then, the outputpull-down transistor cannot discharge unnecessary charges when suppliedto the output terminal due to noise or the like, resulting in amalfunction of erroneous activation of gate lines.

To solve the problem, the aforementioned paper by S. Y. Yoon, et al.presents a gate driver circuit in which dual output pull-downtransistors are provided in parallel for an output terminal of a unitshift register and are alternately activated/deactivated by each frameso that the gate electrode of one of the output pull-down transistors isnot continuously biased.

However, such dual output pull-down transistors provided for a unitshift register requires dual circuits (pull-down driving circuits) fordriving the dual pull-down transistors to be provided in the unit shiftregister, which raises a concern about resultant increased consumptionpower.

SUMMARY OF THE INVENTION

An object of the present invention is to prevent malfunctions of shiftregisters while suppressing increase in consumption power to achieveimproved driving capability.

According to the present invention, the shift register includes a clockterminal and an output terminal, a first transistor configured to supplya clock signal input to the clock terminal to the output terminal, andsecond and third transistors both configured to discharge the outputterminal. The first, second and third transistors have their controlelectrodes connected to first, second and third nodes, respectively. Theshift register further includes a fourth transistor connected between afirst control terminal to which a predetermined first control signal isinput and the second node, a fifth transistor connected between a secondcontrol terminal to which a predetermined second control signal is inputand the third node, and a driving circuit configured to alternatelydrive the second and third transistors on the basis of the first andsecond control signals. The fourth and fifth transistors each have onemain electrode connected to a control electrode of each other in acrossed manner.

When the driving circuit alternately drives the second and thirdtransistors on the basis of the first and second control signals, thefifth and sixth transistors are also alternately turned on/off. Thecontrol electrode of a deactivated one of the second and thirdtransistors is thereby fixed to a predetermined level. This can preventthe threshold voltages of the second and third transistors from beingshifted, which achieves improved operational reliability. Further, sincethe fifth and sixth transistors are connected to the first and secondtransistors, respectively, they are turned on/off with reduced power,which suppresses increase in consumption power.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram illustrating the configuration of adisplay apparatus according to the present invention;

FIG. 2 is a block diagram illustrating an exemplary configuration of agate-line driving circuit employing unit shift registers according tothe invention;

FIG. 3 is a circuit diagram illustrating the configuration of aconventional unit shift register;

FIG. 4 is a timing chart of an operation of the gate-line drivingcircuit shown in FIG. 2;

FIG. 5 is a block diagram illustrating another exemplary configurationof a gate-line driving circuit employing unit shift registers accordingto the invention;

FIG. 6 is a timing chart of an operation of the gate-line drivingcircuit shown in FIG. 5;

FIG. 7 is a circuit diagram illustrating the configuration of a unitshift register according to a first preferred embodiment of theinvention;

FIG. 8 is a timing chart illustrating the operation of the unit shiftregister according to the first preferred embodiment;

FIGS. 9A and 9B are diagrams for explaining the operation of the unitshift register according to the first preferred embodiment;

FIG. 10 is a circuit diagram illustrating the configuration of a unitshift register according to a second preferred embodiment of theinvention;

FIG. 11 is a circuit diagram illustrating the configuration of a unitshift register according to a third preferred embodiment of theinvention;

FIG. 12 is a circuit diagram illustrating the configuration of a unitshift register according to a fourth preferred embodiment of theinvention;

FIGS. 13 and 14 are circuit diagrams each illustrating the configurationof a unit shift register according to a fifth preferred embodiment ofthe invention;

FIG. 15 is a circuit diagram illustrating the configuration of a unitshift register according to a sixth preferred embodiment of theinvention;

FIGS. 16A and 16B are diagrams for explaining the operation of the unitshift register according to the sixth preferred embodiment;

FIGS. 17 and 18 are circuit diagrams each illustrating the configurationof a unit shift register according to a seventh preferred embodiment ofthe invention; and

FIGS. 19 and 20 are circuit diagrams each illustrating the configurationof a unit shift register according to an eighth preferred embodiment ofthe invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be describedhereinbelow referring to the accompanied drawings. To avoid repeated andredundant description, elements having the same or correspondingfunctions are indicated by the same reference characters in thedrawings.

First Preferred Embodiment

FIG. 1 is a schematic block diagram illustrating the configuration of adisplay apparatus according to the present invention. The overallconfiguration of a liquid crystal display 10 is shown as anrepresentative example of the display apparatus.

The liquid crystal display 10 is provided with a liquid crystal arraypart 20, a gate-line driving circuit (scanning-line driving circuit) 30and a source driver 40. As will be described later explicitly, a shiftregister according to the present embodiment is mounted on the gate-linedriving circuit 30.

The liquid crystal array part 20 includes a plurality of pixels 25arrayed in a matrix. The columns of pixels (hereinafter also referred toas “pixel lines”) are respectively provided with gate lines GL₁, GL₂, .. . (hereinafter also generically referred to as a “gate line GL”), andthe rows of pixels (hereinafter also referred to as “pixel rows”) arerespectively provided with data lines DL₁, DL₂, . . . (hereinaftergenerically referred to as a “data line DL”). FIG. 1 representativelyshows pixels 25 of the first and second rows in the first column andcorresponding gate line GL₁ and data lines DL₁ and DL₂.

Each pixel 25 has a pixel switching device 26 disposed between acorresponding data line DL and a pixel node Np, and a capacitor 27 and aliquid crystal display device 28 connected in parallel between the pixelnode Np and a common electrode node NC. The crystal orientation in theliquid crystal display device 28 changes depending on the voltagedifference between the pixel node Np and common electrode node NC, andin response to this change, the display luminance of the liquid crystaldisplay device 28 changes. Accordingly, the luminance of each pixel 25can be controlled by a display voltage transmitted to the pixel node Npvia the data line DL and pixel switching device 26. In other words, anintermediate voltage difference between a voltage differencecorresponding to the maximum luminance and a voltage differencecorresponding to the minimum luminance is applied between the pixel nodeNp and common electrode node NC, whereby halftone luminance can beobtained. Therefore, setting display voltages stepwise, grayscaleluminance can be obtained.

The gate-line driving circuit 30 sequentially selects and drives a gateline GL in a predetermined scanning cycle. Each pixel switching device26 has its gate electrode connected to a corresponding gate line GL.While a certain gate line GL is selected, the pixel switching device 26is brought into the conducting state in each pixel 25 connected to theselected gate line GL, whereby the pixel node Np is connected to acorresponding data line DL. Then, the display voltage transmitted to thepixel node Np is held by the capacitor 27. Generally, the pixelswitching device 26 is constructed from a TFT formed on a substrate ofthe same insulator as the liquid crystal display device 28 (a glasssubstrate, a resin substrate or the like).

The source driver 40 is provided to output display voltages set stepwiseby a display signal SIG which is an N-bit digital signal, to the datalines DL. As an example, the display signal SIG is assumed to be a 6-bitsignal including display signal bits DB0 to DB5. With such 6-bit displaysignal SIG, 2⁶=64 levels of gray can be displayed in each pixel 25.Further, a display of approximately 260 thousand colors can be achievedby forming one color display unit by three pixels of R (Red), G (Green)and B (Blue).

As shown in FIG. 1, the source driver 40 includes a shift register 50,data latch circuits 52, 54, a gradation voltage generating circuit 60, adecoder circuit 70 and an analog amplifier 80.

In the display signal SIG, the display signal bits DB0 to DB5corresponding to the display luminance of respective pixels 25 areserially generated. In other words, each of the display signal bits DB0to DB5 with each timing indicates the display luminance of any one pixel25 in the liquid crystal array part 20.

The shift register 50 gives an instruction to the data latch circuit 52to capture the display signal bits DB0 to DB5 in synchronization with acycle during which the settings of the display signal SIG are changed.The data latch circuit 52 sequentially captures serially-generateddisplay signals SIG to latch display signals SIG for one pixel line.

A latch signal LT input to the data latch circuit 54 is activated withtiming when display signals SIG for one pixel line are captured by thedata latch circuit 52. In response to this, the data latch circuit 54captures the display signals SIG for one pixel line latched by the datalatch circuit 52 at that time.

The gradation voltage generating circuit 60 is formed by 63 resistordividers connected in series between a high voltage VDH and a lowvoltage VDL, for generating 64 levels of gradation voltages V1 to V64,respectively.

The decoder circuit 70 decodes display signals SIG latched by the datalatch circuit 54, and based on the result of decoding, selects voltagesto be respectively output to decoder output nodes Nd1, Nd2, . . .(generically referred to as a “decoder output node Nd”) from among thegradation voltages V1 to V64, and outputs the selected voltages.

As a result, display voltages (selected from among the gradationvoltages V1 to V64) corresponding to the display signals SIG for onepixel line latched by the data latch circuit 54 are output to thedecoder output node Nd at the same time (in parallel). FIG. 1representatively shows the decoder output nodes Nd1 and Nd2corresponding to the data line DL₁ of the first row and the data lineDL₂ of the second row, respectively.

The analog amplifier 80 outputs analog voltages corresponding to displayvoltages output from the decoder circuit 70 to the decoder output nodesNd1, Nd2, . . . , to the data lines DL₁, DL₂, . . . , respectively.

The source driver 40 repeatedly outputs display voltages correspondingto a series of display signals SIG for one pixel line to the data lineDL in a predetermined scanning cycle, and the gate-line driving circuit30 sequentially drives the gate lines GL₁, GL₂, . . . in synchronizationwith the scanning cycle. Accordingly, image display based on the displaysignals SIG is provided on the liquid crystal array part 20.

FIG. 1 shows an example of the liquid crystal display 10 with thegate-line driving circuit 30 and source driver 40 formed integrally withthe liquid crystal array part 20, however, the gate-line driving circuit30 and source driver 40 may be provided as an external circuit of theliquid crystal array part 20.

FIG. 2 shows the configuration of the gate-line driving circuit 30. Thegate-line driving circuit 30 includes a plurality of unit shiftregisters SR₁, SR₂, SR₃, SR₄, . . . connected in cascade (hereinafter,the unit shift registers SR₁, SR₂, . . . will generically be called a“unit shift register SR”). The unit shift register SR is provided oneeach for one pixel line, i.e., one gate line GL.

A clock generator 31 shown in FIG. 2 is provided to input three phaseclock signals CLK1, CLK2 and CLK3, shifted in phase with each other, tothe unit shift register SR of the gate-line driving circuit 30. Theseclock signals CLK1, CLK2 and CLK3 are controlled to be sequentiallyactivated with timing synchronized with the scanning cycle of thedisplay apparatus.

Each unit shift register SR includes an input terminal IN, an outputterminal OUT, a clock terminal CK and a reset terminal RST. As shown inFIG. 2, either one of the clock signals CLK1, CLK2 and CLK3 output fromthe clock generator 31 is supplied to the clock terminal CK and resetterminal RST of each unit shift register SR, respectively. The unitshift register SR has its output terminal OUT connected to a gate lineGL. That is, a signal output to the output terminal OUT (output signal)is a horizontal (or vertical) scanning pulse for activating the gateline GL.

A start pulse corresponding to the head of each frame period of an imagesignal is input to the input terminal IN of the unit shift register SR₁of the first stage. To the input terminal IN of each of the unit shiftregisters SR of the second and following stages, an output signal fromthe immediately preceding stage is input. In other words, the inputterminal IN of the unit shift register SR of the second or subsequentstage is connected to the output terminal OUT of the unit shift registerSR of the immediately preceding stage.

In the gate-line driving circuit 30 of such configuration, each unitshift register SR transmits an input signal received from theimmediately preceding stage (output signal from the immediatelypreceding stage) to a corresponding gate line GL and to a unit shiftregister SR of the immediately succeeding stage while shifting the inputsignal in synchronization with the clock signals CLK1, CLK2 and CLK3(operation of the unit shift register SR will be described later indetail). As a result, a series of unit shift registers SR serve as whatis called a gate-line driving unit for sequentially activating gatelines GL with timing based on the predetermined scanning cycle.

For ease of description of the present invention, a conventional unitshift register will now be described. FIG. 3 is a circuit diagramillustrating the configuration of the conventional unit shift registerSR. In the gate-line driving circuit 30, the respective unit shiftregisters SR connected in cascade have substantially the sameconfiguration. Therefore, the configuration of one unit shift registerSR will be described below as a representative example. Transistorsconstituting the unit shift register SR are all field-effect transistorsof the same conductivity type, and are all assumed to be N-type TFTs inthe present embodiment.

As shown in FIG. 3, the conventional unit shift register SR includes afirst power terminal S1 to which a low supply voltage VSS is supplied,and second and third power terminals S2 and S3 to which a high supplyvoltage VDD is supplied, respectively, in addition to the input terminalIN, output terminal OUT, clock terminal CK and reset terminal RSTalready shown in FIG. 2. While the same potential (VDD) is supplied toboth the second and third power terminals S2 and S3 in this example,different potentials may be supplied only if those potentials aresufficient for driving the transistors Q1 and Q2, respectively. In thefollowing description, the low supply voltage VSS will be defined as areference potential of the circuit (=0V); in practical use, however, areference potential is determined with reference to a voltage of datawritten in pixels. For example, the high supply voltage VDD may be setat 1 7V, and the low supply voltage VSS may be set at −12V.

The output stage of the unit shift register SR includes a transistor Q1connected between the output terminal OUT and clock terminal CK and atransistor Q2 connected between the output terminal OUT and first powerterminal S1. In other words, the transistor Q1 is an output pull-uptransistor for supplying the clock signal input to the clock terminal CKto the output terminal OUT, and the transistor Q2 is an output pull-downtransistor for supplying the level at the first power terminal S1 to theoutput terminal OUT. Hereinafter, a node to which the gate (controlelectrode) of the transistor Q1 constituting the output stage of theunit shift register SR is connected will be defined as a node N1 (firstnode), and a node to which the gate (control electrode) of thetransistor Q2 is connected will be defined as a node N2 (second node).

A capacitive element C is provided between the gate and source of thetransistor Q1 (i.e., between the output terminal OUT and node N1). Atransistor Q3 is connected between the node N1 and second power terminalS2, and has its gate connected to the input terminal IN. Transistors Q4and Q5 are connected between the node N1 and first power terminal S1.The transistor Q4 has its gate connected to the reset terminal RST, andthe transistor Q5 has its gate connected to the node N2.

A diode-connected transistor Q6 is connected between the node N2 andthird power terminal S3. A transistor Q7 is connected between the nodeN2 and first power terminal S1, and has its gate connected to the nodeN1. The transistor Q7 is defined as having a driving capability (currentflowing capability) sufficiently higher than that of the transistor Q6.In other words, the transistor Q7 has an on-state resistance lower thanthat of the transistor Q6. Accordingly, as the gate of the transistor Q7rises in level, the node N2 drops in level; conversely, as the gate ofthe transistor Q7 drops in level, the node N2 rises in level. That is,the transistors Q6 and Q7 constitute an inverter in which the node N1serves as an input node and the node N2 serves as an output node. Theinverter is called “a ratio inverter” whose operation is defined by theratio between the on-state resistances of the transistors Q6 and Q7.This inverter serves as a “pull-down driving circuit” which drives thetransistor Q2 for pulling down the level at the output terminal OUT.

A specific operation of the unit shift register SR shown in FIG. 3 willnow be discussed. Since the respective unit shift registers SRconstituting the gate-line driving circuit 30 operate substantially inthe same manner, the operation of a unit shift register SR_(n) of then-th stage will be discussed as a representative example.

For ease of description, it is assumed that the clock terminal CK of theunit shift register SR_(n) receives the clock signal CLK1 and the resetterminal RST receives the clock signal CLK3. This case corresponds to,e.g., the unit shift registers SR₁ and SR₄ shown in FIG. 2. An outputsignal from the unit shift register SR_(n) is defined as G_(n), and anoutput signal from a unit shift register SR of the immediately preceding(n−1)th stage is defined as G_(n−1). Threshold voltages of transistorsconstituting the unit shift register SR are all assumed to have the samevalue, Vth.

In the initial state, it is assumed that the node N1 is at the L (low)level (VSS), and the node N2 is at the H level (VDD−Vth). Hereinafter,this state will be called a “reset state”. It is also assumed that theclock terminal CK (clock signal CLK1), reset terminal RST (clock signalCLK3) and input terminal IN (output signal G_(n−1) from the immediatelypreceding stage) are all at the L level. In this reset state, thetransistor Q1 is off (cut-off state) and the transistor Q2 is on(conducting state). Accordingly, the output terminal OUT (output signalG_(n)) is kept at the L level regardless of the level at the clockterminal CK (clock signal CLK1). That is, the gate line GL_(n) connectedto this unit shift register SR_(n) is in the non-selected state.

Starting from that state, the output signal G_(n−1) from the immediatelypreceding stage, when raised to the H level, is input to the inputterminal IN of the unit shift register SR to turn on the transistor Q3.At this time, the node N2 is at the H level, and thus, the transistor Q5is also on, however, the node N1 rises in level since the transistor Q3is defined as having a driving capability sufficiently higher than thatof the transistor Q5 and having an on-state resistance sufficientlylower than that of the transistor Q5.

The transistor Q7 thereby starts conducting, causing the node N2 to dropin level. Then, the transistor Q5 increases in resistance, causing thenode N1 to rapidly rise in level to sufficiently turn on the transistorQ7. As a result, the node N2 drops to the L level (VSS), the transistorQ5 turns off, and the node N1 rises to the H level (VDD−Vth). In suchstate where the node N1 is at the H level and the node N2 is at the Llevel (hereinafter this state will be called a “set state”), thetransistor Q1 is on, and the transistor Q2 is off. Thereafter, theoutput signal G_(n−1) from the immediately preceding stage returns tothe L level to turn off the transistor Q3, but the node N1 is broughtinto a floating state, whereby this set state is further maintained.

In the set state, the transistor Q1 is on and the transistor Q2 is off.Thus, when the clock signal CLK1 input to the clock terminal CKsubsequently rises to the H level, the output terminal OUT rises inlevel. At this time, the node N1 is stepped up by a certain voltage by acoupling through the capacitive element C and gate-channel capacitanceof the transistor Q1 (therefore, the node N1 may also be called “astep-up node”). Accordingly, the gate-source voltage of the transistorQ1 is maintained higher than the threshold voltage (Vth) even when theoutput terminal OUT rises in level, so that the transistor Q1 ismaintained at a low impedance. Therefore, the output signal G_(n)quickly varies in level along with the level at the clock terminal CK.Particularly when the gate-source voltage of the transistor Q1 issufficiently high, the transistor Q1 operates in the non-saturatedregion (a non-saturation operation), causing no loss by the thresholdvoltage, which causes the output terminal OUT to rise to the same levelas the clock signal CLK1. Accordingly, the output signal G_(n) is at theH level only during a period in which the clock signal CLK1 is at the Hlevel, at which time the gate line GL_(n) is activated to be broughtinto a selected state. Then, when the clock signal CLK1 returns to the Llevel, the output signal G_(n) quickly returns to the L level followingthat, which causes the gate line GL_(n) to be discharged to return to anon-selected state.

Thereafter, when the clock signal CLK3 input to the reset terminal RSTrises to the H level, the transistor Q4 is turned on to cause the nodeN1 to drop to the L level. The transistor Q7 accordingly turns off tocause the node N2 to rise to the H level. That is, the unit shiftregister SR returns to the reset state in which the transistor Q1 is offand the transistor Q2 is on (therefore, the node N2 may also be called a“reset node”).

Giving a summary of the above-described operation, the unit shiftregister SR is in the reset state unless a signal (start pulse or outputsignal G_(n−1) from the immediately preceding stage) is input to theinput terminal IN, and the transistor Q1 is kept off and the secondtransistor Q2 is kept on, so that the output terminal OUT (gate lineGL_(n)) is maintained at the L level (VSS) with low impedance. When asignal is input to the input terminal IN, the unit shift register SR isswitched into the set state. Since the transistor Q1 is on and thesecond transistor Q2 is off in the set state, the output terminal OUT(output signal G_(n)) is at the H level during a period in which thesignal input to the clock terminal CK (clock signal CLK1) is at the Hlevel. Thereafter, when a signal (clock signal CLK3) is input to thereset terminal RST, the original reset state is brought about.

A plurality of unit shift registers SR each operating as described aboveare connected in cascade as shown in FIG. 2 to constitute the gate-linedriving circuit 30. Then, the input signal (start pulse) input to theinput terminal IN of the unit shift register SR of the first stage istransmitted to unit shift registers SR₂, SR₃, . . . in sequence whilebeing shifted with timing synchronized with the clock signals CLK1, CLK2and CLK3 as shown in the timing chart of FIG. 4. The gate-line drivingcircuit 30 can thereby drive the gate lines GL₁, GL₂, GL₃, . . . insequence in a predetermined scanning cycle.

While the above example shows the case in which the plurality of unitshift registers SR operate on the basis of three phase clock signals,two phase clock signals may be used for operation. FIG. 5 illustratesthe configuration of the gate-line driving circuit 30 in that case.

In that case, the gate-line driving circuit 30 also includes a pluralityof unit shift registers SR connected in cascade. Specifically, each ofthe unit shift registers SR has its input terminal IN connected to theoutput terminal OUT of a unit shift register SR of the immediatelypreceding stage, except that the input terminal IN of the unit shiftregister SR₁ of the first stage receives a start pulse as an inputsignal.

The clock generator 31 in this case outputs two phase clock signals CLKand /CLK of opposite phases to each other. Either of the clock signalsCLK and /CLK is alternately input to the clock terminal CK of each ofthe unit shift registers SR such that each unit shift register SR andits immediately succeeding unit shift register SR receive clock signalsof opposite phases to each other, respectively. As shown in FIG. 5, eachof the unit shift registers SR has the reset terminal RST connected tothe output terminal OUT of a unit shift register SR of a succeedingstage (in this example, the immediately succeeding stage).

The operation of a unit shift register SR in the gate-line drivingcircuit 30 configured as shown in FIG. 5 will be described. Theoperation of the unit shift register SR_(n) of the n-th stage will alsobe discussed as a representative example. For ease of description, it isassumed that the clock terminal CK of the unit shift register SR_(n)receives the clock signal CLK. This case corresponds to, e.g., the unitshift registers SR₁ and SR₃ shown in FIG. 5. An output signal from theunit shift register SR_(n) is defined as G_(n), and output signals froma unit shift register SR_(n−1) of the immediately preceding (n−1)thstage and a unit shift register SR_(n+1) of the immediately succeeding(n+1)th stage are defined as G_(n−1) and G_(n+1), respectively.

In the initial state, the reset state is assumed in which the node N1 isat the L level (VSS) and the node N2 is at the H level (VDD−Vth). It isalso assumed that the clock terminal CK (clock signal CLK), resetterminal RST (output signal G_(n+1) from the immediately succeedingstage) and input terminal IN (output signal G_(n−1) from the immediatelypreceding stage) are all at the L level.

Starting from that state, the output signal G_(n−1) from the immediatelypreceding stage, when raised to the H level, is input to the inputterminal IN of the unit shift register SR_(n) to turn on the transistorQ3, causing the node N1 to rise in level. The transistor Q7 therebystarts conducting, causing the node N2 to drop in level. Then, thetransistor Q5 increases in resistance, causing the node N1 to rapidlyrise in level, so that the transistor Q7 sufficiently turns on. The nodeN2 in turn drops to the L level (VSS) to turn off the transistor Q5,causing the node N1 to rise to the H level (VDD−Vth). As a result, theset state is brought about in which the transistor Q1 is on and thetransistor Q2 is off.

Then, when the clock signal CLK rises to the H level to cause the outputterminal OUT to rise in level, the node N1 rises in level by a certainvoltage by the coupling induced by the capacitive element C andgate-channel capacitance of the transistor Q1. Therefore, the outputsignal G_(n) varies in level along with the level at the clock terminalCK. During a period in which the clock signal CLK is at the H level, theoutput signal G_(n) is also at the H level, causing the gate line GL_(n)to be activated (brought into the selected state). Thereafter, when theclock signal CLK returns to the L level, the output signal G_(n) alsoreturns to the L level, causing the gate line GL_(n) to return to thenon-selected state.

After the output signal G_(n) is transmitted to the unit shift registerSR_(n+1) of the immediately succeeding stage, the output signal G_(n+1)therefrom, when raised to the H level, is input to the reset terminalRST to turn on the transistor Q4, causing the node N1 to drop to the Llevel. The transistor Q7 accordingly turns off, causing the node N2 torise to the H level. That is, the unit shift register SR_(n) returns tothe reset state in which the transistor Q1 is off and the transistor Q2is on.

As described, in the case of the gate-line driving circuit 30 configuredas shown in FIG. 5, the operation of each of the unit shift registers SRis substantially the same as in a configuration as shown in FIG. 2except that the reset terminal RST receives the output signal G_(n+1)from the immediately succeeding stage.

The above-described operation is carried out in sequence by theplurality of unit shift registers SR₁, SR₂, . . . connected in cascadeas shown in FIG. 5. Accordingly, the input signal (start pulse) input tothe input terminal IN of the unit shift register SR1 of the first stageis transmitted to the unit shift registers SR₂, SR₃, . . . in sequencewhile being shifted with timing synchronized with the clock signals CLKand /CLK. As a result, the gate-line driving circuit 30 can therebydrive the gate lines GL₁, GL₂, GL₃, . . . in sequence in synchronizationwith the clock signals CLK and /CLK as shown in the timing chart of FIG.6.

In the configuration shown in FIG. 5, however, the reset terminal RSTreceives the output signal G_(n+1) from the immediately succeedingstage. Accordingly, each of the unit shift registers SR returns to thereset state (i.e., the above-described initial state) only after a unitshift register SR of the immediately succeeding stage is operated atleast once. Each of the unit shift registers SR cannot carry out thenormal operation as shown in FIG. 6 unless it undergoes the reset state.Therefore, the configuration shown in FIG. 5 requires carrying out adummy operation in which a dummy input signal is transmitted through theunit shift registers SR from the first to the last stages prior to thenormal operation. Alternatively, a reset transistor may additionally beprovided between the node N2 and third power terminal S3 (high supplyvoltage) of each of the unit shift registers SR to carry out a resetoperation of compulsory charging the node N2 prior to the normaloperation. In that case, however, the provision of a reset signal lineis additionally required.

The aforementioned problem of malfimction of the conventional unit shiftregister SR will now be described in detail. In the followingdescription, each transistor constituting the unit shift register SR isassumed to be an a-Si TFT.

The lowermost part of the timing chart of FIG. 6 shows voltage waveformsat the node N2 of the unit shift register SR₁ in the gate-line drivingcircuit 30 shown in FIG. 5. As described above, when a signal input tothe input terminal IN (start pulse or output signal G_(n−1) from theimmediately preceding stage) rises to the H level, the node N2 drops tothe L level, but immediately returns to the H level by a signal input tothe reset terminal RST (output signal G_(n+1) from the immediatelysucceeding stage) to be maintained at the H level for about one frameperiod (about 16 ms) (although not shown, this behavior is also seen inthe case of FIG. 2). That is, the gate of each of the transistors Q2 andQ5 is continuously positively biased (dc-biased) for about one frameperiod, which is repeatedly carried out in each frame. Accordingly, whenthe unit shift register SR is formed of a-Si TFTs, the threshold voltageof the transistors Q2 and Q5 is shifted to the positive direction,resulting in degraded driving capability.

When the transistor Q5 in the reset state is degraded in drivingcapability, charges occurred at the node N1 due to the noise resultingfrom, for example, an overlap capacitance between the gate andsource/drain of the transistor Q1, and the like cannot be dischargedquickly, which may cause the node N1 to rise in level. In such case, thetransistor Q1 in the off state decreases in resistance, causing chargesto be unnecessarily supplied to the output terminal OUT when the clocksignal CLK rises to the H level. Further, when the transistor Q2 hasdegraded driving capability at this time, charges at the output terminalOUT occurred by the noise cannot be discharged quickly, causing theoutput terminal OUT to rise in level. That is, a malfunction that thegate line which should be in the non-selected state is brought into theselected state occurs, resulting in a display malfunction of the liquidcrystal display 10.

As described earlier, the aforementioned paper by S. Y. Yoon, et al.presents a gate driver circuit in which dual output pull-downtransistors are provided for a unit shift register and are alternatelyactivated/deactivated by each frame so that the gate electrode of one ofthe output pull-down transistors is not continuously biased. This canavoid the display malfunction. However, dual circuits (pull-down drivingcircuits) for driving the dual pull-down transistors need to be providedin the unit shift register, which raises a concern about resultantincreased consumption power. Hereinafter, a shift register according tothe present invention capable of solving the aforementioned malfunctionwill be described.

FIG. 7 is a circuit diagram illustrating the configuration of the unitshift register SR according to the first preferred embodiment of thepresent invention. As shown in the drawing, the output stage of the unitshift register SR includes the transistor Q1 connected between theoutput terminal OUT and clock terminal CK and transistors Q2A and Q2Bboth connected between the output terminal OUT and first power terminalS1. More specifically, the transistor Q1 is a first transistor forsupplying a clock signal input to the clock terminal CK to the outputterminal OUT, and the transistors Q2A and Q2B are second and thirdtransistors, respectively, for supplying the level at the first powerterminal S1 to the output terminal OUT. As shown in FIG. 7, a node towhich the gate (control electrode) of the transistor Q1 is defined as anode N1, a node to which the gate of the transistor Q2A is connected isdefined as a node N2A, and a node to which the gate of the transistorQ2B is connected is defined as a node N2B.

The capacitive element C is provided between the gate and source of thetransistor Q1, i.e., between the node N1 and output terminal OUT. Thetransistor Q3 is connected between the node N1 and second power terminalS2, and has its gate connected to the input terminal IN. Transistors Q4,Q5A and Q5B are connected between the node N1 and first power terminalS1. The transistor Q4 has its gate connected to the reset terminal RST.The transistor Q5A has its gate connected to the node N2A, and thetransistor Q5B has its gate connected to the node N2B.

The unit shift register SR according to the present embodiment includesa first control terminal CTA to which a predetermined first controlsignal VFR is input and a second control terminal CTB to which a secondcontrol signal /VFR is input. The first control signal VFR and secondcontrol signal /VFR are complementary to each other, and are generatedby a driver controller (not shown) for driving the gate-line drivingcircuit 30. Preferably, these first control signal VFR and secondcontrol signal /VFR are controlled to switch in level (i.e., alternate)during a blanking period between frames of a display image, and arecontrolled to switch in level by each frame of a display image, forexample.

A transistor Q8A is connected between the first control terminal CTA andnode N2A, and a transistor Q8B is connected between the second controlterminal CTB and node N2B. The transistor Q8A has its gate connected tothe drain of the transistor Q8B (node N2B), and the transistor Q8B hasits gate connected to the drain of the transistor Q8A (node N2A). Inother words, the transistors Q8A and Q8B constitute what is called aflip-flop circuit each having one main electrode (drain in thisembodiment) connected to the control electrode (gate) of each other in acrossed manner.

A diode-connected transistor Q6A is connected between the node N2A andfirst control terminal CTA. A transistor Q7A having its gate connectedto the node N1 is connected between the node N2A and first powerterminal S1. These transistors Q6A and Q7A constitute a ratio inverterin which the node N1 serves as an input node and the node N2A serves asan output node; however, unlike a typical inverter, the first controlsignal VFR is supplied as power supply.

A diode-connected transistor Q6B is connected between the node N2B andsecond control terminal CTB. A transistor Q7B having its gate connectedto the node N1 is connected between the node N2B and first powerterminal S1. These transistors Q6B and Q7B constitute a ratio inverterin which the node NI serves as an input node and the node N2B serves asan output node; however, unlike a typical inverter, the second controlsignal /VFR is supplied as power supply. Hereinafter, the inverterformed of the transistors Q6A and Q7A will be called “a first inverter”,and the inverter formed of the transistors Q6B and Q7B will be called “asecond inverter”.

FIG. 8 is a timing chart illustrating the operation of the unit shiftregister SR according to the first preferred embodiment. Hereinafter,the unit shift register SR according to the present embodiment shown inFIG. 7 will be described with reference to FIG. 8. While the unit shiftregister SR shown in FIG. 7 is applicable to either configuration of thegate-line driving circuits 30 shown in FIGS. 2 and 5, the followingdescription is addressed to the operation of the gate-line drivingcircuit 30 formed of cascade-connected unit shift registers SR as shownin FIG. 5. The first control signal VFR and second control signal /VFRare input to all cascade-connected unit shift registers SR.

The operation of the unit shift register SR_(n) of the n-th stage willbe discussed as a representative example. It is assumed that the clockterminal CK of the unit shift register SR_(n) receives the clock signalCLK. An output signal from the unit shift register SR_(n) is defined asG_(n), and output signals from the unit shift register SR_(n−1) of theimmediately preceding (n−1)th stage and the unit shift register SR_(n+1)of the immediately succeeding (n+1)th stage are defined as G_(n−1) andG_(n+1), respectively.

For ease of description, the H level of each the clock signals CLK and/CLK, first control signal VFR and second control signal /VFR is allassumed to be equal to the high supply voltage VDD. The first controlsignal VFR and second control signal /VFR are assumed to be controlledto switch in level by each frame of a display image. Further, Thresholdvoltages of transistors constituting the unit shift register SR are allassumed to have the same value, Vth.

As shown in FIG. 8, the first control signal VFR rises to the H leveland the second control signal /VFR drops to the L level at time tl inthe blanking period (not shown) between frame periods. Since the firstcontrol signal VFR is input to the first control terminal CTA of theunit shift register SRn, the drain and gate of the transistor Q6A risesfrom VSS to VDD, causing the transistor Q6A to turn on. In other words,power is supplied to the first inverter formed of the transistors Q6Aand Q7A, so that the first inverter is activated. Since the transistorQ5B is on, and the node N1 is at the L level (i.e., non-selected stateof the gate line GL_(n)) at this time, the transistor Q7A is off,causing the node N2A to rise in level.

Since the second control signal /VFR is input to the second controlterminal CTB, the drain and gate of the transistor Q6B drops from VDD toVSS. In other words, power is not supplied to the second inverter formedof the transistors Q6B and Q7B. As the transistor Q6B serves as a diodein which the direction from the second control terminal CTB to the nodeN2B is the forward direction, charges at the node N2B are not dischargedthrough the transistor Q6B. As described above, however, since the nodeN2A rises in level and the source of the transistor Q8B (second controlterminal CTB) is at VSS, the transistor Q8B is turned on, causing thenode N2B to drop to the L level (VSS). The transistor Q8A is accordinglyturned off, causing the node N2A to rise to the H level (VDD−Vth). Thatis, the potential distribution in the flip-flop circuit formed of thetransistors Q8A and Q8B is as shown in FIG. 9A after time t1.

Since the second inverter is not activated during a period in which thefirst control signal VFR is at the H level and the second control signal/VFR is at the L level, the node N2B is fixed to the L level. Therefore,the transistors Q2B and Q5B are not biased at the gate, and thus aredeactivated during that period. In other words, in the unit shiftregister SR during that period, a combination of the transistors Q1,Q2A, Q3, Q4, Q5A, Q6A and Q7A constitutes a circuit equivalent to theunit shift register SR shown in FIG. 3, and is capable of performing asimilar operation.

That is, the output signal G_(n−1) from the immediately preceding stage,when raised to the H level at time t2, is input to the input terminalIN, causing the transistor Q3 to turn on. At this time, the transistorQ5A also turns on, however, the node N1 rises to the H level (VDD−Vth)since the transistor Q3 is defined as having an on-state resistancesufficiently lower than that of the transistor Q5A.

In the first inverter formed of the transistors Q6A and Q7A, the node N1serves as an input node, and the node N2A serves as an output node.Thus, when the node N1 rises to the H level, the node N2A drops to the Llevel. The transistors Q2A and Q5A are accordingly turned off. Here,since the first inverter is a ratio inverter, the potential of output atthe L level is a value determined by the ratio between on-stateresistances of the transistors Q6A and Q7A. That is, the transistors Q6Aand Q7A are both turned on during a period in which the node N2A is atthe L level, causing a short circuit current to flow from the firstcontrol terminal CTA to the first power terminal S1 through thetransistors Q6A and Q7A, whereby a certain amount of power is consumed.

Thereafter, when the output signal G_(n−1) from the immediatelypreceding stage returns to the L level, the transistor Q3 is turned off,but the node N1 is brought into a floating state, so that the node N1 ismaintained at the H level. Then, when the clock signal CLK rises to theH level at time t3, the clock signal CLK at the H level is supplied tothe output terminal OUT since the transistor Q1 is on, causing theoutput signal Gn to rise to the H level. At this time, the node N1 isstepped up by a certain voltage by the capacitive coupling between thecapacitive element C and gate-channel capacitance of the transistor Q1,along with the rise in level of the output signal G_(n). Accordingly,the source-gate voltage of the transistor Q1 is maintained high, so thatthe transistor Q1 is maintained at a low impedance. Therefore, theoutput signal G_(n) quickly follows the level of the clock signal CLK.The output signal G_(n) thus quickly returns to the L level when theclock signal CLK returns to the L level.

When the output signal G_(n+1) from the immediately succeeding stagerises to the H level at time t4, it is input to the reset terminal RST,turning the transistor Q4 on. As a result, the node N1 drops to the Llevel, turning the transistor Q7A off, which causes the node N2A toreturn to the H level (VDD−Vth). Thereafter, this state is maintaineduntil the first control signal VFR and second control signal /VFR areinverted in level at time t5 in the next blanking period.

Then, when the first control signal VFR drops to the L level, and thesecond control signal /VFR rises to the H level at time t5, the secondinverter formed of the transistors Q6B and Q7B is activated contrary towhat is was, causing the node N2B to rise to the H level. The transistorQ8A is accordingly turned on, and the first inverter is not activatedsince the drain of the transistor Q6A (first control terminal CTA) is atVSS, causing the node N2A to drop to the L level (VSS).

That is, the potential distribution in the flip-flop circuit formed ofthe transistors Q8A and Q8B is as shown in FIG. 9B after time t5. Duringthat period, the transistors Q2A and Q5A are not biased at the gate, andthus are deactivated. Further, the first inverter does not operate withno power being supplied. Therefore, in the unit shift register SR, acombination of the transistors Q1, Q2B, Q3, Q4, Q5B, Q6B and Q7Bconstitutes a circuit equivalent to the unit shift register SR shown inFIG. 3, whereby similar operations to those at time t1 to t5 areperformed.

As described, the unit shift register SR shown in FIG. 7 is capable ofperforming similar operations as in the conventional shift registershown in FIG. 3. In addition, the pair of the transistors Q2A and Q5Aand the pair of the transistors Q2B and Q5B are alternately deactivatedevery time the first control signal VFR and second control signal /VFRare inverted, which prevents the gates of those transistors from beingdc-biased. This can prevent the unit shift register SR frommalfunctioning due to shifts in threshold voltage of a-Si TFTs, whichachieves improved operational reliability.

In the unit shift register SR according to the present embodimentincluding the first inverter formed of the transistors Q6A and Q7A andthe second inverter formed of the transistors Q6B and Q7B, the first andsecond inverters are alternately activated every time the first controlsignal VFR and second control signal /VFR complementary to each otherare inverted. In other words, the first and second inverters serve as adriving circuit for alternately driving the transistors Q2A and Q2B onthe basis of the first control signal VFR and second control signal/VFR. Since both the first and second inverters are not activated at thesame time, consumption power is equivalent to that of a shift registerincluding a single inverter, which prevents increase in consumptionpower.

In the unit shift register SR according to the present embodiment, thetransistors Q8A and Q8B constitute a flip-flop circuit, however, unlikea typical flip-flop circuit, the first control signal VFR and secondcontrol signal /VFR are input to the sources of the transistors Q8A andQ8B, respectively. For instance, at time t2, the transistor Q8B needs tobe turned on by the output from the inverter formed of the transistorQ7A and Q8A, but the source of the transistor Q8A (first control signalVFR) is at VDD at that time. Accordingly, even when a small currentflows from the inverter formed of the transistors Q6A and Q7A, the nodeN2A sufficiently rises in level to turn on the transistor Q8B, whichprevents increase in consumption power.

Assuming that the source potential of the transistors Q8A and Q8B to befixed to VSS as in the typical flip-flop circuit, the transistor Q6Aneeds to have sufficiently greater driving capability than thetransistor Q8A in order to cause the node N2A to sufficiently rise inlevel, resulting in increased consumption power. Further, since theoperation of a ratio inverter is defined by the ratio between theon-state resistances of two transistors, increasing the transistor Q6Ain driving capability requires the transistor Q7A to be also increasedin driving capability, which causes consumption power of the inverter tobe increased. The unit shift register shown in FIG. 7 also solves thisproblem.

Another advantage given by inputting the first control signal VFR andsecond control signal /VFR to the sources of the transistors Q8A andQ8B, respectively, is as follows: during a period in which the firstcontrol signal VFR is at the H level and the second control signal /VFRis at the L level, the potential distribution in the transistors Q8A andQ8B is as shown in FIG. 9A except a selected period in which the gateline GL is selected, whereby the gate of the transistor Q8A isnegatively biased with respect to the source. Conversely, during aperiod in which the first control signal VFR is at the L level and thesecond control signal /VFR is at the H level, the potential distributionin the transistors Q8A and Q8B is as shown in FIG. 9B except theselected period in which the gate line GL is selected, whereby the gateof the transistor Q8B is negatively biased with respect to the source.

As described above, the gates of the transistors Q8A and Q8B arenegatively biased with respect to the sources at regular intervals,which effectively prevents the threshold voltage of the transistors Q8Aand Q8B from being shifted in the positive direction. This can suppressdegradation in driving capability of the transistors Q8A and Q8B, sothat the L level potential (VSS) with low impedance can be supplied tothe nodes N2A and N2B. This in result achieves a great advantage inpreventing the threshold voltage of the transistors Q2A, Q2B, Q5A andQ5B from being shifted.

While it has been described above that the first control signal VFR andsecond control signal /VFR are switched in level (i.e., alternate) in ablanking period by each frame, the cycle may be arbitrarily determined.For instance, the switching may be carried out every two or more frames.However, too long cycle may cause the threshold voltages of thetransistors Q2A, Q2B, Q5A and Q5B to be shifted significantly, so thatthe effects of the present invention may not be obtained sufficiently.Therefore, it is preferable that the switching be made about every frameas described in the present embodiment. The timing of alteration may notnecessarily be within a blanking period, however, switching duringoperation of the unit shift register SR may cause voltage variations inthe circuit, which may result in a malfunction such as delay inoperating speed caused by a parasitic capacitance, and the like.Accordingly, it is preferable that the switching be made in a blankingperiod as in the above example.

Second Preferred Embodiment

In the unit shift register SR according to the first preferredembodiment, the transistor Q6A constituting the first inverter and thetransistor Q6B constituting the second inverter are bothdiode-connected. In other words, the transistor Q6A has its gate anddrain both connected to the first control terminal CTA to which thefirst control signal VFR is input, and the transistor Q6B has its gateand drain both connected to the second control terminal CTB to which thesecond control signal /VFR is input.

FIG. 10 is a circuit diagram illustrating the configuration of a unitshift register SR according to a second preferred embodiment. As shownin the drawing, the transistor Q6A has its gate connected to the firstcontrol terminal CTA, but its drain connected to the third powerterminal S3 to which the high supply voltage VDD is input. Similarly,the transistor Q6B has its gate connected to the second control terminalCTB, but its drain connected to the third power terminal S3.

More specifically, according to the present embodiment, the firstinverter is formed of the transistor Q6A connected between the node N2Aand third power terminal S3, with its gate receiving the first controlsignal VFR and the transistor Q7A connected between the node N2A andfirst power terminal S1, with its gate connected to the node N1. Thesecond inverter is formed of the transistor Q6B connected between thenode N2B and third power terminal S3, with its gate receiving the secondcontrol signal /VFR and the transistor Q7B connected between the nodeN2B and first power terminal S1, with its gate connected to the node N1.

The unit shift register SR according to the present embodiment differsfrom the unit shift register SR according to the first preferredembodiment (FIG. 7) in that the high supply voltage VDD is supplied tothe drains of the transistors Q6A and Q6B, but almost the same inoperation. Therefore, the present embodiment achieves similar effects asthose in the first preferred embodiment.

With the configuration shown in FIG. 10, the load capacity of the firstcontrol signal VFR and second control signal /VFR is smaller than in theconfiguration shown in FIG. 3, which is advantageous in that consumptionpower is further reduced.

Third Preferred Embodiment

FIG. 11 is a circuit diagram illustrating the configuration of a unitshift register SR according to a third preferred embodiment. Accordingto the present embodiment, the transistor Q3 has its drain connected tothe input terminal IN, not to the power source. This can reduce the areaoccupied by a wire for power supply. However, it should be noted thatthe input terminal IN is connected to the output terminal OUT of theimmediately preceding stage, which increases a load on the output stageof each unit shift register SR, so that the speed of circuit operationmay be reduced.

While FIG. 11 shows an example of the present embodiment applied to thecircuit according to the first preferred embodiment (FIG. 7), thepresent embodiment may also be applied to the circuit according to thesecond preferred embodiment (FIG. 10).

Fourth Preferred Embodiment

A field effect transistor including TFT is a device which conducts byelectric connection between the drain and source made by a conductivechannel formed directly under a gate electrode with a gate insulationfilm interposed therebetween within a semiconductor substrate when avoltage not less than a threshold voltage is applied to the gateelectrode. Accordingly, a field effect transistor in the conductingstate has a certain static capacitance (gate capacitance) between thegate and channel, that is, the field effect transistor may also functionas a capacitive element with its channel and gate electrode within thesemiconductor substrate serving as both electrodes and the gateinsulation film serving as a dielectric layer. Such capacitive elementis called “a MOS (Metal-Oxide Semiconductor) capacitive element”.

FIG. 12 is a circuit diagram illustrating the configuration of a unitshift register SR according to a fourth preferred embodiment. While thecapacitive element C is provided between the drain and source of thetransistor Q1 in the above-described preferred embodiments forefficiently stepping up the node N1, it is replaced by the gatecapacitance of the transistor Q1 in the present embodiment. In thiscase, the capacitive element C is not required, as shown in the circuitdiagram of FIG. 12.

The insulation film to be a dielectric layer of a capacitive elementformed in a semiconductor integrated circuit generally has the samethickness as a gate insulation film of a transistor. Accordingly, whenreplacing a capacitive element by a gate capacitance of a transistor, atransistor having the same area as the capacitive element may be used.Specifically, increasing the gate width of the transistor Q1 asnecessary in FIG. 12 achieves an operation similar to that performed bythe above-described preferred embodiments. Further, increasing the gatewidth of the transistor Q1 increases its driving capability, resultingin increased rising and falling rates of the output signal, whichproduces another advantageous effect of achieving higher speedoperation.

While FIG. 12 shows the example of the present embodiment applied to thecircuit according to the first preferred embodiment (FIG. 7), thepresent embodiment may also be applied to the circuits according to thesecond and third preferred embodiments (FIGS. 10, 11) and the like.

Fifth Preferred Embodiment

The present embodiment presents a configuration for speeding up theoperation of the unit shift registers SR according to theabove-described preferred embodiments. FIG. 13 is a circuit diagramillustrating the configuration of a unit shift register SR according toa fifth preferred embodiment. As shown in the drawing, a transistor Q11Ahaving its gate connected to the reset terminal RST is provided betweenthe node N2A and first control terminal CTA (in parallel to thetransistor Q6A), and a transistor Q12A having its gate connected to theinput terminal IN is provided between the node N2A and first powerterminal S1 (in parallel to the transistor Q7A). Further, a transistorQ11B having its gate connected to the reset terminal RST is providedbetween the node N2B and second control terminal CTB (in parallel to thetransistor Q6B), and a transistor Q12B having its gate connected to theinput terminal IN is provided between the node N2B and first powerterminal S1 (in parallel to the transistor Q7B). The configuration ofthe present embodiment is similar to that of the first preferredembodiment (FIG. 7) except these transistors.

For instance, it is assumed that the first control signal VFR is at theH level and the second control signal /VFR is at the L level. In thiscase, when the output signal G_(n−1) from the immediately precedingstage rises to the H level, the transistor Q12A is turned on, causingthe node N2A serving as the output node of the first inverter to drop tothe L level at high speeds. The transistor Q5A is accordingly turnedoff, causing the node N1 to rise to the H level at high speeds. When theoutput signal G_(n+1) from the immediately succeeding stage rises to theH level, the transistor Q11A is turned on, causing the node N2A to riseto the H level at high speeds. The transistor Q5A is accordingly turnedon, causing the node N1 to drop to the L level at high speeds.

As described, the nodes N1 and N2A are shifted in level at high speedsby the action of the transistors Q11A and Q12A. Similarly, thetransistors Q11B and Q12B speed up level shift at the nodes N1 and N2B.Therefore, the present embodiment achieves a higher speed operation thanin the first preferred embodiment.

The above-described technique is applicable to the unit shift registerSR according to the second preferred embodiment (FIG. 10). In that case,as shown in FIG. 14, transistors Q11A and Q13A connected in series areprovided between the node N1 and third power terminal S3 (in parallel tothe transistor Q6A). The transistor Q11A has its gate connected to thereset terminal RST, and the transistor Q13A has its gate connected tothe first control terminal CTA. Similarly, transistors Q11B and Q13Bconnected in series is provided between the node N1 and third powerterminal S3 (in parallel to the transistor Q6B). The transistor Q11B hasits gate connected to the reset terminal RST, and the transistor Q13Bhas its gate connected to the second control terminal CTB.

Similarly to the case of FIG. 13, the nodes N1 and N2A are shifted inlevel at high speeds by the action of the transistors Q11A, Q12A andQ13A. Similarly, the transistors Q11B, Q12B and Q13B speed up levelshift at the nodes N1 and N2B. Therefore, the present embodimentachieves a higher speed operation than in the first preferredembodiment. The transistor Q13A prevents the node N2A to be maintainedat the L level during a period in which the first control signal VFR isat the L level from being charged by the transistor Q11A. Similarly, thetransistor Q13B prevents the node N2B to be maintained at the L levelduring a period in which the second control signal /VFR is at the Llevel from being charged by the transistor Q11B.

In the present embodiment, as the transistors Q11A, Q12A, Q13A, Q11B,Q12B and Q13B increase in driving capability, the effect of high speedoperation increases. Since a short circuit current dose not flow throughthe transistors Q11A, Q12A, Q11B and Q12B, consumption power isincreased only slightly by increasing the gate width. Therefore, a highspeed operation can be achieved while preventing increase in consumptionpower.

The third and fourth preferred embodiments are also applicable to thepresent embodiment.

Sixth Preferred Embodiment

FIG. 15 is a circuit diagram illustrating the configuration of a unitshift register SR according to a sixth preferred embodiment. Accordingto the present embodiment, main electrodes of the transistors Q8A andQ8B connected to each other are sources, unlike in the first preferredembodiment. In other words, while the circuit shown in FIG. 7 turnson/off the transistors Q8A and Q8B by outputs of the first and secondinverters, respectively, the turning on/off is carried out by the firstand second control signals VFR and /VFR, respectively, in the presentembodiment. The circuit is similar in operation to the circuit shown inFIG. 7 except this point. Therefore, the present embodiment achievessimilar effects as those in the first preferred embodiment.

In the unit shift register SR shown in FIG. 15, during a period in whichthe first control signal VFR is at the H level and the second controlsignal /VFR is at the L level, the potential distribution in thetransistors Q8A and Q8B is as shown in FIG. 16A except the selectedperiod in which the gate line GL is selected, whereby the gate of thetransistor Q8A is negatively biased with respect to the source.Conversely, during a period in which the first control signal VFR is atthe L level and the second control signal /VFR is at the H level, thepotential distribution in the transistors Q8A and Q8B is as shown inFIG. 16B except the selected period in which the gate line GL isselected, whereby the gate of the transistor Q8B is negatively biasedwith respect to the source.

According to the present embodiment, as described above, the gates ofthe transistors Q8A and Q8B are also negatively biased with respect tothe sources at regular intervals, which effectively prevents thethreshold voltage of the transistors Q8A and Q8B from being shifted inthe positive direction. This can suppress degradation in drivingcapability of the transistors Q8A and Q8B, so that the L level potential(VSS) of low impedance can be supplied to the nodes N2A and N2B. This inresult achieves a great advantage in preventing the threshold voltage ofthe transistors Q2A, Q2B, Q5A and Q5B from being shifted.

The aforementioned third to fifth preferred embodiments may also beapplied to the present embodiment.

Seventh Preferred Embodiment

While the alternate driving of the transistors Q2A and Q2B is performedby the two inverters in the above preferred embodiments, a similaroperation is carried out by a single inverter in the present embodiment.

FIG. 17 is a circuit diagram illustrating the configuration of a unitshift register SR according to a seventh preferred embodiment. In theunit shift register SR, the driving circuit for driving the transistorsQ2A and Q2B includes an inverter formed of the transistors Q6 and Q7,the transistor Q9A connected between the output node of that inverter(defined as a node N3) and node N2A and the transistor Q9B connectedbetween the nodes N3 and N2B. The transistor Q9A has its gate connectedto the first control terminal CTA to which the first control signal VFRis input, and the transistor Q9B has its gate connected to the secondcontrol terminal CTB to which the second control signal /VFR is input.In the inverter, the transistor Q6 is diode-connected and is connectedbetween the node N3 and third power terminal S3, and the transistor Q7having its gate connected to the node N1 is connected between the nodeN3 and first power terminal SI.

In the present embodiment, during a period in which the first controlsignal VFR is at the H level and the second control signal /VFR is atthe L level, the transistor Q9A is turned on and the transistor Q9B isturned off, causing the output node of the inverter, i.e., the node N3to be electrically connected to the node N2A. In other words, duringthat period, the transistor Q2A is activated while the transistor Q2B isdeactivated. Conversely, in a period in which the first control signalVFR is at the L level and the second control signal /VFR is at the Hlevel, the transistor Q9A is turned off and the transistor Q9B is turnedon, causing the node N3 to be electrically connected to the node N2B. Inother words, during that period, the transistor Q2B is activated whilethe transistor Q2A is deactivated. In this manner, the transistors Q9Aand Q9B serve as a switching circuit for connecting the output node(node N3) of the inverter formed of the transistors Q6 and Q7alternately to the nodes N2A and N2B.

In the present embodiment, the pair of the transistors Q2A and Q5A andthe pair of the transistors Q2B and Q5B are alternately deactivatedevery time the first control signal VFR and second control signal /VFRare inverted, which prevents the gates of those transistors from beingdc-biased. This can prevent a malfunction due to shifts in thresholdvoltage of a-Si TFTs, which achieves improved operational reliability.In addition, since the circuit of the present embodiment drives thetransistors Q2A and Q2B using a single inverter, increase in consumptionpower is suppressed.

Further, the number of transistors whose gates are connected to the nodeN1 is smaller than, for example, in the first preferred embodiment,which reduces the gate capacitance of transistors connected to the nodeN1. Thus, the parasitic capacitance at the node N1 is reduced,increasing the step-up amount at the node N1 by the clock terminal CK,which results in higher driving capability of the transistor Q1 when theoutput signal G_(n) is output. This produces an advantage of higherspeed operation.

Furthermore, the fifth preferred embodiment may be applied to theinverter formed of the transistors Q6 and Q7. FIG. 18 shows the circuitdiagram in that case. As shown, a transistor Q11 having its gateconnected to the reset terminal RST is provided between the node N3 andthird power terminal S3 (in parallel to the transistor Q6), and atransistor Q12 having its gate connected to the input terminal IN isprovided between the node N3 and first power terminal S1 (in parallel tothe transistor Q7). This allows still higher speed operation.

It should be noted that not only the fifth preferred embodiment but alsothe third, fourth and sixth preferred embodiments are applicable to thepresent embodiment.

Eighth Preferred Embodiment

In the circuit according to the first preferred embodiment (FIG. 7),when the output terminal OUT (output signal G_(n)) rises to the H level,the transistors Q7A and Q7B are both on since the node N1 is at the Hlevel. Thus, the nodes N2A and N2B are both at the L level with lowimpedance. In contrast, in the circuit according to the seventhpreferred embodiment (FIG. 17), when the first control signal VFR is atthe H level and the second control signal /VFR is at the L level, forinstance, the node N2B is at the L level with high impedance. When theoutput signal Gn rises from the L level to the H level in that state,the node N2B rises in level by a coupling through a gate-to-drainoverlap capacitance of the transistor Q2B. Then, the transistor Q2B mayconduct to cause the output signal G_(n) at the H level todisadvantageously drop.

FIG. 19 is a circuit diagram illustrating the configuration of a unitshift register SR according to an eighth preferred embodiment. As shown,the unit shift register SR according to the present embodiment furtherincludes, in the circuit according to the seventh preferred embodiment(FIG. 17), a transistor Q10A connected between the node N2A and firstpower terminal S1 and a transistor Q10B connected between the node N2Band second power terminal S2. The transistors Q10A and Q10B have theirgates both connected to the output terminal OUT.

In the unit shift register SR according to the present embodiment, thetransistors Q10A and Q10B are both on during a period in which theoutput signal G_(n) is at the H level, allowing the nodes N2A and N2B tobe at the L level with low impedance. Thus, the transistors Q2A and Q2Bcan be maintained in the off state without fail during that period,which can solve the aforementioned problem.

FIG. 19 shows the configuration in which the transistors Q10A and Q10Bare provided for the circuit shown in FIG. 17, however, as shown in FIG.20, these transistors may be provided for the circuit shown in FIG. 18.This can produce an advantage of achieving higher speed operation of theunit shift register SR as in the circuit shown in FIG. 18.

Further, the third, fourth and sixth preferred embodiments may also beapplied to the present embodiment.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing from the scope of theinvention.

1. A shift register comprising: a clock terminal and an output terminal;a first transistor configured to supply a clock signal input to saidclock terminal to said output terminal; and second and third transistorsboth configured to discharge said output terminal, wherein said first,second and third transistors have their control electrodes connected tofirst, second and third nodes, respectively, said shift register furthercomprising: a fourth transistor connected between a first controlterminal to which a predetermined first control signal is input and saidsecond node; a fifth transistor connected between a second controlterminal to which a predetermined second control signal is input andsaid third node; and a driving circuit configured to alternately drivesaid second and third transistors on the basis of said first and secondcontrol signals, wherein said fourth and fifth transistors each have onemain electrode connected to a control electrode of each other in acrossed manner.
 2. The shift register according to claim 1, wherein saiddriving circuit includes: a first inverter in which said first nodeserves as an input node and said second node serves as an output node;and a second inverter in which said first node serves as an input nodeand said third node serves as an output node, wherein said first andsecond inverters are alternately activated on the basis of said firstand second control signals.
 3. The shift register according to claim 2,wherein said first inverter includes: a diode-connected sixth transistorconnected between said second node and said first control terminal; anda seventh transistor connected between said second node and said firstpower terminal, said seventh transistor having a control electrodeconnected to said first node, and said second inverter includes: adiode-connected eighth transistor connected between said third node andsaid second power terminal; and a ninth transistor connected betweensaid third node and said first power terminal, said ninth transistorhaving a control electrode connected to said first node.
 4. The shiftregister according to claim 2, wherein said first inverter includes: asixth transistor connected between said second node and said secondcontrol terminal, said sixth transistor having a control electrode towhich said first control signal is input; and a seventh transistorconnected between said second node and said first power terminal, saidseventh transistor having a control electrode connected to said firstnode, and said second inverter includes: an eighth transistor connectedbetween said third node and said second power terminal, said eighthtransistor having a control electrode to which said second controlsignal is input; and a ninth transistor connected between said thirdnode and said first power terminal, said ninth transistor having acontrol electrode connected to said first node.
 5. The shift registeraccording to claim 1, wherein said driving circuit includes: an inverterin which said first node serves as an input node; and a switchingcircuit configured to electrically connect an output node of saidinverter alternately to said second and third nodes.
 6. The shiftregister according to claim 5, wherein said switching circuit includes:a sixth transistor connected between the output node of said inverterand said second node, said sixth transistor having a control electrodeto which said first control signal is input; and a seventh transistorconnected between the output node of said inverter and said third node,said seventh transistor having a control electrode to which said secondcontrol signal is input.
 7. The shift register according to claim 1,further comprising a capacitive element connected between said firstnode and said output terminal.
 8. The shift register according to claim1, wherein said first and second control signals are complementary toeach other.
 9. A shift register comprising a plurality of shiftregisters connected in cascade, each being defined in claim
 1. 10. Animage display apparatus comprising a gate-line driving circuit formed ofa plurality of shift registers connected in cascade, wherein each ofsaid plurality of shift registers includes: a clock terminal and anoutput terminal; a first transistor configured to supply a clock signalinput to said clock terminal to said output terminal; and second andthird transistors both configured to discharge said output terminal,said first, second and third transistors have their control electrodesconnected to first, second and third nodes, respectively, said shiftregister further includes: a fourth transistor connected between a firstcontrol terminal to which a predetermined first control signal is inputand said second node; a fifth transistor connected between a secondcontrol terminal to which a predetermined second control signal is inputand said third node; and a driving circuit configured to alternatelydrive said second and third transistors on the basis of said first andsecond control signals, and said fourth and fifth transistors each haveone main electrode connected to a control electrode of each other in acrossed manner.
 11. The image display apparatus according to claim 10,wherein said first and second control signals are controlled to beswitched in level in a blanking period between frames of a displayimage.
 12. The image display apparatus according to claim 11, whereinsaid first and second control signals are controlled to be switched inlevel by each frame of a display image.